MEMS wafer level package

ABSTRACT

An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer fabrication and packaging technology. The device is contained within a hermetic cavity produced by bonding a silicon wafer with active circuits to an etched silicon wafer having cavities which surround each device, and bonding the two wafer by either thin film glass seal or by solder seal. The etched wafer and thin film sealing allow conductors to be kept to a minimum length and matched for improved electrical control of the circuit. Further, the device has capability for a ground ring in the solder sealed device. The devices may be packaged in plastic packages with wire bond technology or may be solder connected to an area array solder connected package.

FIELD OF THE INVENTION

[0001] The present invention relates in general to semiconductorpackaging, and more specifically to a package for amicro-electromechanical device.

BACKGROUND OF THE INVENTION

[0002] Micro-electromechanical devices (MEMS) make use of semiconductortechnology to fabricate microscopic mechanisms on the surface of asemiconductor wafer. These devices have a wide range of uses, such asaccelerometers, pressure sensors, actuators, and other types of sensors.Due to their size, the microscopic mechanisms are extremely vulnerableto damage from handling, to particles, to air flow and moisture;therefore, packaging of the devices presents many more challenges thanconventional integrated circuits. Many of the devices have moving partswhich requires a cavity surrounding the device co allow the device tomove freely, and so for the most part, the devices have been packaged inceramic or metal packages having a cavity. However, these options areboth an expensive, poorly automatic process and they do not resolve theissue of particles from the sawing process during separating theindividual devices on a wafer. Further, they are not necessarilyoptimized for device reliability and performance.

[0003] In an attempt to circumvent the problem, such devices have beenencapsulated at the wafer level, before separating into individualchips. This provides a technique for avoiding damage to unprotectedmechanisms which occurs during the separation and packaging process. Invery early work on wafer level packaging, the devices were covered witha thick layer of silicon dioxide during the final wafer processing step.This, of course, was completely unsatisfactory for devices having movingparts.

[0004] A more satisfactory solution was provided by V. J. Adams, et alin U.S. Pat. No. 5,323,051 which is incorporated herein by reference.This patent describes a wafer having active devices in a silicon wafersubstrate with a second silicon wafer adhered to the substrate to form acap, and a pattern of walls on the cap formed from frit glass whichsurround the individual devices. The walls are patterned to surroundeach device, allowing a hermetic package around each unit after the capand substrate are bonded by firing the glass. Holes in the cap wafer areprovided for electrical connection to the electrodes which pass throughthe frit glass wall seals. Following bonding of the two wafers, thedevices are separated with minimal concern for debris from the sawingprocess, and each device is housed in a hermetic cavity. There are anumber of advantages to this prior art approach, including matchedthermal expansion coefficient between the silicon wafer substrate andcap silicon wafers, protection of the devices, and the potential forassembly of the individual devices into low cost elastic packages.

[0005] However, fabrication processes for the existing art are notcompatible with assembly techniques or equipment which is in well knownin state-of-the-art wafer fabrication and/or plastic assemblyfacilities. Instead, it makes use of screen printing a frit glasscompound, which has previously been used in the fabrication of ceramicpackages and substrates, but is atypical of current high volumesemiconductor processing facilities. Further, a process which relies ona relatively thick patterned frit glass across the surface of a wafer issubject to non-uniformity in stand-off height, as well as to run out orbleed of the molten glass into active areas of the devices. Potentialbleed of the glass film into the active circuitry requires that largeperimeters be allowed to avoid such a problem, thereby decreasing thenumber of devices that can be assembled on a given substrate. The largeperimeter area required to avoid run-out of the glass also necessitatesthat the conductor lengths between active circuit and contact pad belong, thereby increasing the lead inductance.

[0006] A need exists for a method of packaging micro-electromechanicaldevices fabricated on a semiconductor wafer before the wafer is dicedinto individual chips, by making use of state-of-the-art high volumemanufacturing techniques from either wafer fabrication or from plasticpackage assembly. The method must provide a well controlled cavitywithin which micro-machined parts are free to move, have thermalcharacteristics which closely match that of the device, allow access forelectrical contacts, and be optimized for device performance.

SUMMARY OF THE INVENTION

[0007] The present invention provides an improved wafer levelencapsulated micro-electromechanical device and method of manufacture-for devices fabricated on a semiconductor wafer. The active devices areencapsulated at the wafer level before dicing by adhering a cap waferhaving cavities patterned by anisotropic etching of the cap. Thecavities correspond to the location of the active circuits, and theunetched portions provide walls which are topped by a thin film of glasssputtered through a patterned mask. The cap wafer is adhered to thesubstrate by reflowing the glass film and forming a hermetic cavityaround each active circuit. Openings for test probes and bond wires areprovided through the cap wafer prior to aligning the two wafers andreflowing the glass. The assembled wafers are tested electrically inwafer form by probing with conventional test equipment. The testeddevices are subsequently processed using conventional plastic moldedpackage assembly techniques, including dicing with automated saws,attaching the devices to a lead frame, wire bonding through the openingsin the cap, and encapsulating with plastic molding compounds.

[0008] Precision of the etched cavities and walls, coupled with thinfilm glass sealing of the wafers minimizes run-out or bleed of the glassinto active areas, thereby allowing the circuit and contacts to bespaced in close proximity, supporting both higher density of circuits onthe wafers, as well as short contact leads with lower resistivity.

[0009] An alternate method for adhering the substrate and recessed capwafers makes use of solder reflow processing, rather than glass.Advantages include low temperature processing, potential for a groundring surrounding the circuit, and compatibility with area array packageswith solder contacts.

[0010] Both embodiments make use of manufacturing equipment andprocesses currently in production at state-of-the-art wafer fabricationand packaging assembly sites.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a cross sectional view of a device encapsulated within awafer level package having an etched cap and thin film glass bonding.

[0012]FIG. 2 is a perspective cross sectional view of deviceencapsulated within a semiconductor wafer level package having fritglass walls. (Prior art)

[0013]FIG. 3a is a cross sectional view of the cap wafer prior tobonding to a substrate.

[0014]FIG. 3b is a top view of a portion of a cap wafer.

[0015]FIG. 4a shows the cross section of a plastic package housing adevice encapsulated within a wafer level package.

[0016]FIG. 4b is a cut away top view of a plastic package housing adevice encapsulated within a wafer level package.

[0017]FIG. 5 is a cross sectional view of a device encapsulated within awafer level package having an etched cap and solder seal between the capand substrate wafers.

[0018]FIG. 6a shows a cross section of the insulator and metal layers ona substrate wafer prior to solder sealing to a cap wafer.

[0019]FIG. 6b is a cross sectional view of the insulators and metallayers on a cap wafer prior to solder sealing to a cap wafer.

[0020]FIG. 7 is a cross sectional view of a device encapsulated within awafer level package having etched cap and solder seal between the capand substrate, and having a solder ball attached to the conductor.

[0021]FIG. 8 is a top view of a cap wafer having a metal ring capable ofproviding a ground ring.

DETAILED DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 shows a cross sectional view of micro-electromechanical(MEM) devices wherein the semiconductor devices 112 are encapsulated ina cavity within a wafer level package 121 assembly. In the preferredembodiment, the device 112 is an RF circuit with amicro-electromechanical switch controlled by capacitance changes. Thedevice 112 is fabricated on a silicon substrate wafer 111, whichcomprises a wafer of silicon before the wafer has been diced into aplurality of distinct chips. A cap wafer 116 is prepared by providing aplurality of holes 118 which extend completely through the cap wafer atpredetermined locations. A pattern of etched cavities 115 havingpredetermined dimensions whose locations correspond to a pattern ofdevices 112 on the substrate wafer. A thin film of glass 114 isdeposited on the unattached portion of the cap wafer, i.e., the top 125portions of the cavity wall 124. The pattern is such that the device 112will be completely surrounded by the cavity walls 124, but the moveableparts of the MEM will be free to move in all directions.

[0023] Holes 118 in the cap wafer 116 formed by drilling or anisotropicetching allow access to contact pads 113 a extending from conductorleads 113 electrically coupled to the device. The device circuits may beelectrically tested by means of test probes positioned through the holes118 in the cap. Subsequently wire bonds will be connected through theholes 118 to the contact pads 113 a as the devices are assembled into afinal package.

[0024] The cap wafer 116 is bonded to the semiconductor substrate wafer111 using the deposited thin film glass 114 as a bonding agent. Thebonding comprises aligning the two wafers and heating the cap wafer withglass, and the substrate wafer to a sufficiently high temperature tomelt the glass, and subsequently cooling to solidify the glass. In thisway, a semiconductor wafer level package is formed as part of a cappedwafer structure with the device 112 hermetically sealed in a cavity 115of predetermined dimensions formed by a combination of the semiconductorsubstrate, the cap wafer and cavity walls with thin film of glass.Glasses suitable for thin film deposition and reflowing are well knownto those versed in the art.

[0025] For comparison, FIG. 2 shows a cross sectional view of one deviceof known art wherein a semiconductor device 12 is encapsulated within awafer level package 21. Device 12 is fabricated on a semiconductorsubstrate wafer 11 which comprises a wafer of semiconductor materialbefore the wafer has been diced into a plurality of distinct chips. Acap wafer 16 is prepared by providing a plurality of holes 18 whichextend completely through the cap wafer. A plurality of frit glass walls14 having predetermined dimensions is deposited on cap wafer 16. Thepredetermined pattern is such that the device 12 will be completelysurrounded by frit glass walls. Frit glass walls 14 have been depositedby silk screening a slurry of a mixture of organic cinder and frit glassthrough a patterned screen, the organic binder burned off and the classfired at a temperature to allow bonding between the two wafers.

[0026] If the device of known art 12 is an electromechanical devicehaving moving parts, it is necessary that the frit glass walls 14 bemaintained at sufficient height to allow unrestricted movement of thedevice. Changes in height of the frit glass walls due to both organicburn out and to glass slump during firing are difficult to controluniformly across the entire surface of the wafers. Further, the weightof the cap wafer adds to the probability of the glass walls collapsingduring firing of the frit glass.

[0027] Significant difficulty may be expected due to excessive glassflow and run-out into both the active device 12 areas and into theelectrical contact areas 13 with the volume of frit glass required toform cavity walls. This property of glass reflow and run-out would inturn require that the spaces between side walls formed by frit glass andthe active and contact areas be relatively large to avoid glasscontamination, and thereby forcing long conductor paths with increasedresistivity.

[0028] As illustrated in FIG. 1, cavity walls 124 of the currentinvention formed by anisotropic etching of silicon cap wafer 116 arespaced in close proximity to both the active circuit 112 and to theconductor contact pads 113 a. Metal traces 113 patterned during devicefabrication form a plurality of electrodes on the semiconductorsubstrate wafer which provide electrical coupling to the device andterminate in contact pads 113 a. Advantages of very snort conductorlengths are both that the number of devices per wafer is increased, andthat resistance of the conductors is smaller, thus supporting therequirement for controlled electrical parameters.

[0029] Both the silicon substrate 111 and cap 116 wafers are in therange of 0.2 to 0.5 mm thickness and owing to the identical thermalexpansion and modulus properties, stress on the seal glass is kept to aminimum. Cavity walls having been anisotropically etched usingtechniques well known in the industry are in the range of 0.05 to 0.2mm, thickness.

[0030]FIG. 3 provides a schematic cross sectional view of a portion ofthe cap wafer 116 having a first 125 and second 135 major surface. Anarray of holes 118 is drilled or etched completely through a siliconwafer 116. A patterned array of cavities 115 of predetermined dimensionsis by anisotropic etching of the silicon wafer, leaving relatively thinsilicon walls 124 of precise dimensions. A thin film of glass 114 isdeposited by sputtering through a mask having an array of aperturescorresponding to the top surface of the cavity walls 125. The glass film114 is in the range of 0.5 to 5.0 microns. Pattern resolution of theglass is of little significance as long as the top surfaces 125 of thewalls 124 are covered in order to provide a seal between the substrateand cal wafers. The devices are spaced to provide an array of scribestreets 126 for subsequently dicing the assembled wafer into individualdevices. Deposition of the seal glass by sputtering makes use orequipment and processes well known and accepted in the fabrication ofintegrated circuit devices.

[0031]FIG. 3b provides a schematic view of portion of the second surface135 of cap wafer. An array or scribe streets 126 are provided forseparating the assembled devices. Holes 118 through the wafer areprovided within each device area. The dashed lines 127 represent thelocation and area of cavity walls.

[0032] The two wafers are typically aligned by means of locating holesformed in each wafer into which an alignment pin is inserted prior tothe bonding process. The wafers are further aligned optically by visionsystems inserted between the roughly aligned wafers. Vision systems forsimultaneous viewing of an upper and lower device are commonly used inthe industry for aligning flip chip devices. The capped wafer assemblageis introduced into a chamber having controlled environment, as well astemperature profiling and heating capability. While in a controlledatmosphere, the cap wafer and substrate wafer are heated to bond themtogether to form a semiconductor wafer level package. The bondinghermetically seals the capped wafer structure capturing the controlledatmosphere within the cavity. The chamber is cooled at a programmed rateas defined by the glass manufacturer in order to assure minimal stresson the joints. Processing temperature profiles and required atmospherefor various glasses are provided by the glass suppliers, and are knownin the industry. The capped wafer structure is electrically tested andthen diced into a plurality of composite chips by sawing, a method wellknown in the industry. The electrically good devices are then ready forassembly into a final package having external contacts.

[0033]FIG. 4a provides a cross-sectional view of an individual MEMdevice 401 of the preferred embodiment completely assembled in a lowcost high volume plastic package 420. An array of wafer levelencapsulated MEM devices having an active silicon substrate bonded tocap wafer is diced using conventional automated dicing saws, and one ofthe individual electrically good devices attached by an adhesive to alead frame die pad 421. Wire bonds 424 are made through holes in thedevice cap to the contact pads 413 a and attached to inner leads 422 ofthe lead frame. The bonded device is encapsulated by a polymericcompound 425 using injection molding techniques, well known a used inhigh volume production within the industry.

[0034] Processing temperatures for plastic assembly are well below thereflow temperature of the seal glass used to bond the cap and substratewafers. The active device is hermetically sealed and protected fromchemical and particulate contamination.

[0035]FIG. 4b shows a cut away view of a wafer level encapsulated MEMdevice 401 which is diced into individual device, wire bonded, andencapsulated in a plastic package 420. Short on-chip thin filmconductors 413 between the active circuits 401 and contact pads 413 a,short wire bonds 424 and symmetry in the leads 422, as well as allconductors of the entire provide a means for readily controlledelectrical parameters having relatively low resistivity.

[0036] An alternate embodiment of the current invention is shown incross sectional view in FIG. 5. This embodiment provides a MEM 501 waferlevel encapsulated device 512 fabricated on a semiconductor substratewafer 511 before dicing into a plurality of distinct chips. A cap wafer516 is prepared by providing a plurality of holes 518 which extendcompletely through the cap wafer at predetermined locations. A patternof etched cavities 515 having predetermined dimensions whose locationscorrespond to a pattern of devices 512 on a substrate wafer 511. A layerof solder 544 is deposited on the unetched portions of the cap wafer,i.e. the top surface of the cavity walls 524. The pattern is such thatthe device 512 will be completely surrounded by the cavity walls 524,but the moveable parts of the MEM will be free to move in alldirections. Holes 518 in the cap wafer 516 are provided as was the casewith the preferred embodiment. The cap wafer 516 is bonded to thesemiconductor substrate wafer using the solder as the bonding agent toattach the wafers and to seal the cavities.

[0037]FIGS. 6a and 6 b provide more detailed arrangement of the layersof metals and insulators for a solder sealed wafer scale encapsulatedMEM device. In FIG. 6a, conductors 613 between the active circuit 611and the contact cad 613 are insulated from the solder and solderablemetals by deposition a dielectric film 625 of SiO2, Si3N4 orcombination, using the similar materials and technology as thatproviding passivation on the active circuits. The film 625 is patternedand etched to expose the contact pads 613 a and to avoid anyinterference with the MEM operation. A thin film metal layer 630compatible with solders, such as Au or Pd is provided in areas where thesolder seal will bond the substrate to cap wafer. Such solderable metalsrequire an adhesion layer 626 between the insulator and solderablemetals. Typically the adhesion layers known within the industry are Cu,Cr or Ti/W and solderable metals are Pd and Au. The metal layers 626 and630 are deposited by CVD or sputtering and etching using techniques wellknown within the industry, and typically used in flip chip and substrateprocessing.

[0038] In FIG. 6b the semiconductor cap wafer 616 is patterned, holes618 provided and cavities 615 etched as described for the preferredembodiment. As shown in FIG. 6b, the entire wafer is insulated bydepositing a blanket layer 641 of silicon dioxide, nitride orcombination thereof onto the wafer having an array of cavities 630 ofpredetermined dimensions and locations, and holes 618 completely throughthe wafer. An adhesion layer or layers 643, and solderable metal layer642 are deposited by CVD or sputter techniques through apertures in amask corresponding to the top surfaces of the etched walls 624. A layerof solder 644 is deposited by sputtering through a mask onto thepatterned solderable metal or by electroless plating.

[0039] Solders may be either lead containing or lead free materials,with selection of the exact composition determined by reflow temperaturecharacteristics and alpha emissivity sensitivity of the devices. Soldersavailable for sealing the devices can be very low temperature indiummaterials, lead free composites of Sn, Ag, Cu and Sb (Castin), or any ofthe conventional Sn/Pb solders.

[0040] The two wafers are aligned by optical or mechanical means. Theassemblage of wafers is introduced into a controlled environment chamberand the temperature programmed to heat and allow the solder to reflowand seal the individual devices. Temperature and environmentalcomposition are dependent on the solder composition selected. The solderreflow processes are well known in the industry and the specificconditions provided by the manufacturer of solders.

[0041] The wafer assemblage comprising a substrate wafer with active MEMdevices, a cap wafer having an array of cavities and walls formed byanisotropic etching and having solder compatible metals and a solderlayer covering the top surface of the cavity walls, and the wafershaving been bonded by solder reflow are ready for dicing into individualchips and final assembly with external electrical contacts.

[0042] In one embodiment, the contact pads of the semiconductor devicehave only the on-chip metallization as the active device. No insulationor additional metals are provided and as such the device is ready forassembly into a plastic package as previously described for the glasssealed embodiment.

[0043] In yet another embodiment, shown in FIG. 7, the contact padsinclude the following metal layers. Layer 713 a, the same as the on-chipmetallization, an adhesion layer 726 and a solderable metal layer 730.The adhesion and solder compatible layers were deposited by CVD orsputtering and patterned in the same operation as that described in FIG.6a. The solderable metal layer 730 of Au or Pd on the contact pad 713 ais compatible with wire bonding, or as shown in FIG. 7, may be contactedthrough the hole 718 in the cap 716 by a solder ball 750 for joiningdirectly to a substrate for area array packaging, such as BGA (ball gridarray) or CSP (chip scale package).

[0044]FIG. 8 provides a schematic view of portion of the second surface835 of cap wafer. An array of scribe streets 826 are provided forseparating the assembled devices. Holes 818 through the wafer areprovided within each device area. The solid area 827 represent thelocation and area of cavity walls having a top surface covered by anelectrically conductive metal and solder 844. The now conductive toosurface 844 of the cavity walls provides an electrically conductivering, isolated from the active device by the dielectric file, asdescribed previously. In yet another embodiment, the conductive ring iselectrically contacted at preselected locations to form a ground ringfor the active device.

[0045] Some advantages of the solder as compared to class sealing ofwafer scale encapsulated devices are in potentially lower temperatureprocessing, in availability of a electrical around ring in the cap sealaround each device, and that the devices are compatible with newer areaarray packages, such as BGA and CSP having solder contacts to the nextlevel o interconnection.

[0046] It should be understood that while the preferred embodiments havedescribed a wafer level package having semiconductor chip encased insilicon substrate and cap, the method is applicable to a multiple chipswithin each cavity of the wafer level package, forming a multi-chipfunctional device.

[0047] In summary, an improved MEM wafer level encapsulated device andmethod for manufacture of MEM devices fabricated on a semiconductorsubstrate wafer before the wafer is diced into individual devices hasbeen shown. Each individual device is encapsulated in a hermeticenclosure by etching predetermine cavity sizes in a second silicon waferwherein the cavities locations correspond to those of the active deviceon a substrate wafer. The top surfaces of the cavity walls are coveredwith a thin film of glass sputter deposited through apertures in a mask.The two wafers are aligned and the glass reflowed, forming a hermeticseal around each active device. Holes through the cap wafer align tocontact pads on the substrate which are connected electrically to theactive circuits.

[0048] The thin glass minimizes run out of glass, and coupled withnarrow cavity walls, allows conductors between the active circuit andthe exposed contact pads to be kept short, thereby minimizing resistanceof the conductors. The compact design, further, allows fabrication ofmore devices per wafer than with processes which require greaterconductor spacing. Processes and equipment are consistent with thoseused in high volume semiconductor production.

[0049] An alternate process utilizing the same etched cap wafer andsubstrate wafer is described wherein the devices are sealed by solderreflow.

[0050] While ore erred embodiments and some alternative applications ofthe invention nave been described above, it is understood that variousmodifications may be made from the specific details described hereinwithout departing from the spirit and scope of the invention as setforth in the appended claims.

What is claimed is:
 1. A micro-electromechanical wafer levelencapsulated device, comprising: a plurality of devices fabricated on asemiconductor substrate wafer, a cap wafer fabricated from a siliconwafer, and an array of cavities of predetermined height etched in apattern corresponding to the active devices on said substrate wafer, anda thin film of glass covering the unetched area, a hermetic sealproduced by bonding the cap wafer to the semiconductor wafer using saidthin film glass as a bonding agent such that each of said discretedevices is sealed in a cavity of predetermined dimensions, at least oreconductor formed on the surface of the substrate wafer which provideselectrical coupling to each device fabricated on the substrate wafer,and an array of holes fabricated in the cap wafer which provides accessto each of said conductors from outside the cavity.
 2. Amicro-electromechanical device as in claim 1 wherein the devicecomprises an RF switch.
 3. A micro-electromechanical device as in claim1 wherein said conductors have equal length and resistivity.
 4. Amicro-electromechanical device as in claim 1 wherein said glass is inthe range of 0.5 to 5.0 microns in thickness.
 5. A micro-mechanicaldevice as in claim 1 wherein walls of said cavity comprise silicon inthe range of 0.06 to 0.2 mm thickness.
 6. A RF switchmicro-electromechanical wafer level encapsulated device, comprising: aplurality of devices fabricated on a semiconductor substrate wafer, acap wafer fabricated from a silicon wafer having an array of cavities ofpredetermined height etched in a pattern corresponding to each of theactive devices on said substrate wafer, the walls of said cavities beingin the range of 0.05 to 0.2 mm in thickness, and a thin film of glass inthe range of 0.5 to 5.0 microns thickness covering the unetched area, ahermetic seal produced by bonding the cap wafer to the semiconductorwafer using said thin film glass as a bonding agent such that eachdiscrete device is sealed in a cavity of predetermined dimensions, oneor more conductors of equal length and resistivity formed on the surfaceof the substrate wafer which provides electrical coupling to each devicefabricated on the substrate wafer, an array of holes fabricated in thecap wafer which provides access to each of said conductors from outsidethe cavity.
 7. A micro-electromechanical wafer level encapsulateddevice, as in claim 1 wherein said device comprises multiple chips.
 8. Aplastic encapsulated micro-electromechanical device comprising; asemiconductor device encapsulated within a cavity in a silicon cap,wherein said cap is bonded to the device substrate by a thin film ofglass, one or more conductors on the device substrate electricallycoupled to the device and extending outside the encapsulated cavity, andeach of which is accessible by a hole in the cap, wire bonds connectionsbetween each of said conductors and a lead frame, and said devices areencapsulated in a plastic molding compound.
 9. A method of forming amicro-electromechanical wafer level encapsulated device, including thesteps of: providing a plurality of devices fabricated on a semiconductorsubstrate wafer having at least one conductor on the surfaceelectrically coupled to each device, providing a cap wafer fabricatedfrom a silicon wafer, having an array of cavities of predeterminedheight etched in a pattern corresponding to the active devices on saidsubstrate wafer, and a thin film of glass covering the unetched area,and at least one hole fabricated in the cap which provides access toeach of said conductors, aligning the substrate wafer and cap wafer,heating to bond the cap wafer to the semiconductor wafer using said thinfilm glass as a bonding agent such that each discrete device is sealedin a cavity of predetermined dimensions, and sawing the wafer assemblageinto individual chips.
 10. A method as in claim 9 wherein cavities insaid cap wafer are formed by anisotropic etching of silicon through aphotolithographic pattern.
 11. A method as in claim 9 wherein glass isdeposited by sputtering through a mask having a predetermined pattern ofapertures.
 12. A method as in claim 9 wherein said thin film glass ispatterned using photolithography and etching.
 13. A method as in claim 9wherein holes in said cap wafer are formed by anisotropic etchingthrough a photolithographic pattern.
 14. A method as in claim 9 whereinthe devices are electrically tested in wafer form by positioning probesthrough holes in the cap wafer and contacting the conductors.
 15. Amicro-electromechanical wafer level encapsulated device, comprising: aplurality of devices fabricated on a semiconductor substrate wafer, acap wafer fabricated from a silicon wafer, having an array of cavitiesof predetermined height etched in a pattern corresponding to the activedevices on said substrate wafer, and a film of solder adhered to a layerof solder compatible metal covering the unetched area, at least oneconductor formed on the surface of the substrate wafer which provideselectrical coupling to each device fabricated on the substrate wafer,said conductors further covered by a dielectric film, and a soldercompatible metal layer, a hermetic seal produced by bonding the capwafer to the semiconductor wafer using said solder as a bonding agentsuch that the device is sealed in a cavity of predetermined dimensions,and an array of holes fabricated in the cap wafer which provides accessto each of said conductors from outside the cavity.
 16. Amicro-electromechanical device as in claim 15 having a solder ballattached to each conductor through said holes in the cap.
 17. Amicro-electromechanical device as in claim 15 having an electricalground ring surrounding each discrete device produced by metal layers onthe cap.
 18. A method of forming micro-electromechanical wafer levelencapsulated devices, including the steps of: providing a plurality ofdevices fabricated on a semiconductor substrate wafer having at leastone conductor on the surface electrically coupled to each device,providing a cap wafer fabricated from a silicon wafer, having an arrayof cavities of predetermined height etched in a pattern corresponding toeach of the active devices on said substrate wafer, a layer of soldercompatible metal and a layer of solder covering the unetched area, andan array of one hole fabricated in the cap which provides access to eachof said conductors, aligning the substrate wafer and cap wafer, bondingthe cap wafer to the semiconductor wafer using said solder and metals asbonding agents such that each discrete device is sealed in a cavity ofpredetermined dimensions, and sawing the wafer assemblage intoindividual devices.
 19. A method as in claim 18 wherein said soldercompatible metals and solder are deposited by sputtering through a masshaving a predetermined pattern of apertures.
 20. A method as in claim 18wherein said solder is deposited by electroless plating.